quartus的延迟为什么这么严重啊该怎么处理

library ieee;
use ieee.std_logic_1164.all;
entity e is
port(
a,b:in std_logic;
y,h,f,yf,yh,hf,yhf:out std_logic
);
end e;
architecture b of e is
begin
process(a,b)
begin 
y<=a and b;
h<=a or b;
f<=not a;
yf<=a nand b;
yh<=a xor b;
hf<=a nor b;
yhf<=not(a xor b);
end process;
end b;