FPGA新手求教,该如何解决

FPGA新手求教
这几天一直在编写常用库，可是今天别写七段显示译码器的时候遇到一个Quartus II 9.0的报错，说我的“=”申明错误。VHDL如下，
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;


entity sn7448 is
  port(lt,rbi:in std_logic;
  datain:in std_logic_vector(3 downto 0);
  bi_rbo:inout std_logic;
  dataout:out std_logic_vector(7 downto 0));
end sn7448;

architecture rt1 of sn7448 is
  signal dataout_1:std_logic_vector(7 downto 0);
  begin 
  bi_rbo<=not(datain(0) and datain(1) and datain(2) and datain(3) and lt and (not rbi));
  process(datain,lt,rbi,bi_rbo)
  begin
  if(lt='1')then
  if(bi_rbo='1')then
  case datain is
  when "0000"=>dataout_1<="00111111";
  when "0001"=>dataout_1<="00000110";
  when "0010"=>dataout_1<="01011011";
  when "0011"=>dataout_1<="01001111";
  when "0100"=>dataout_1<="01100110";
  when "0101"=>dataout_1<="01101101";
  when "0110"=>dataout_1<="01111101";
  when "0111"=>dataout_1<="00000111";
  when "1000"=>dataout_1<="01111111";
  when "1001"=>dataout_1<="01101111";
  when "1010"=>dataout_1<="01110111";
  when "1011"=>dataout_1<="01111100";
  when "1100"=>dataout_1<="00111001";
  when "1101"=>dataout_1<="10011110";
  when "1110"=>dataout_1<="01111001";
  when "1111"=>dataout_1<="01110001";
  when others=>dataout_1<="00000000";
  end case;
  if(rbi='0'and dataout_1="00111111")then
  dataout<="00000000";
  else
  dataout<=dataout_1;
  end if;  
  else 
  dataout<="00000000";
  end if;
  else
  dataout<="11111111";
  end if;
  end process;
end rt1;

调试了一下，发现问题出在红色的语句那里，把红色语句删掉就可以编译通过了。可我是实在看不出这语句哪里不对了，求各位指教。错误信息如下，
Error (10621): VHDL Use Clause error at sn7448.vhd(42): more than one Use Clause imports a declaration of simple name ""="" -- none of the declarations are directly visible

------解决方案--------------------
use ieee.std_logic_unsigned.all;
use ieee.std_logic_signed.all;

这2个别同时用。