您当前的位置: Verilog 区分大小写, 且所有关键字都是小写
1 register = storage
keyword reg; default x; variable that can hold value
2 net = connection
keyword wire; default z; be driven continuously
例 1) D 触发器 (同步复位)
module dff(clk, rst, d, q); //dff with syn reset input clk, rst, d; output q; reg q; always @(posedge clk) begin if (rst) q <= 1'b0; else q <= d; end endmodule
例 2) D 触发器 (异步复位)
module dff(clk, rst, d, q); // dff with asyn reset input clk, rst, d; output q; reg q; always @(posedge clk or posedge rst) begin if (rst) q <= 1'b0; else q <= d; end endmodule
3 continuous assignment
assign data_left = data_right; // right drive left(net)
例 3) mux
assign data_out = select ? data_in1 : data_in0;
4 procedural assignment
1) blocking ("=")
execute sequential
2) nonblocking ("<=")
read (right) -> schedule (left) -> execute (<=)
例 4) synchronizer
reg [1:0] data_sync; always @ (posedge clk or posedge rst) begin if (rst) data_sync <= 2'b00; else data_sync <= {data_sync[0], data_in}; end assign data_out = data_sync[1]; synchronizer